Result description
A loosely-coupled Vector Processing Unit (VPU), compliant with the RISC-V Vector Extension v0.7.1, designed to interface with an out-of-order core and access the memory hierarchy via an AMBA5 CHI RN-I. It features hardware support for memory disambiguation between scalar-vector and vector-vector memory operations, an AXI4-Lite debug interface, and integrated error detection for fault tolerance.
Addressing target audiences and expressing needs
Our needs are
- Collaboration
- Other type of Investment
We specifically need / are looking for
Investments to further advance the technology’s maturity by enhancing its features and developing more sophisticated systems, aiming to support both the research ecosystem and industrial applications.
Target audiences
- Research and Technology Organisations
- Academia/ Universities
- Private Investors
R&D, Technology and Innovation aspects
Current stage description
Compliance with the latest RISC-V Vector specs 1.0.. Silicon proved (Tapeout). Next step increase TRL (7-8)
Result submitted to Horizon Results Platform by BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
