Result description
FPGA platform logic static perimeter architecture is composed of IP blocks common to most FPGA-based systems for communication and access to memory. This includes the FPGA side of the PCIe controller, memory controller and interface for the HBM, and communication blocks and interfaces for nearest-neighbor and remote FPGA communication.
Missions
Addressing target audiences and expressing needs
Our needs are
- Use of research Infrastructure
- Collaboration
- Fellowship to advance my/our research
We specifically need / are looking for
Wwe are looking for early adopters, uses cases, private and public companies/institutions in Risc-v business manufacturing.
Target audiences
- Public or private funding institutions
- Research and Technology Organisations
- Academia/ Universities
R&D, Technology and Innovation aspects
Current stage description
Current stage: integration of the HW components and integration and porting of the SW on the cluster
Next stage: testing and porting new develpment for different FPGA models and different design of the MEEP shell. Testing new RTL design for accelerators.
Result submitted to Horizon Results Platform by BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION