Result description
The DRAC project at BSC has released the second generation of the Lagarto processor series. The design is called DVINO, and it stands for Drac Vector IN-Order and integrates a Lagarto scalar core with a Hydra Vector Processing Unit (VPU).
Missions
Addressing target audiences and expressing needs
Our needs are
- Use of research Infrastructure
- Collaboration
- Fellowship to advance my/our research
We specifically need / are looking for
We are looking for early adopters, uses cases, private and public companies/institutions in Risc-v business manufacturing.
Target audiences
- Public or private funding institutions
- Research and Technology Organisations
- Academia/ Universities
R&D, Technology and Innovation aspects
Current stage description
Current stage: integration of the HW components and integration and porting of the SW on the cluster
Next stage: testing and porting new develpment for different FPGA models and different design of the MEEP shell
Result submitted to Horizon Results Platform by BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION