The KI‑PRO project, funded under the German Federal Ministry of Education and Research with the grant number 16ES1002, ran from October 2019 to March 2023 and was later extended by six months because of pandemic‑related supply‑chain and laboratory disruptions. The initiative was led by the IHP GmbH – Leibniz Institute for Innovative Microelectronics – in close cooperation with the University of Lübeck, which coordinated the project management, and the Technical University of Munich, which supplied key analog components. A RISC‑V based system demonstrator was jointly developed with the University of Lübeck to showcase the practical applicability of the neuromorphic accelerator in a realistic automotive scenario.

Technically, the project achieved the first integration of a resistive random‑access memory (RRAM) crossbar array into a digital accelerator designed for matrix‑vector multiplication (MVM) in artificial‑intelligence workloads. The accelerator, fabricated in IHP’s 130 nm CMOS process, contains a 16 × 16 RRAM crossbar in which each cell can be programmed to one of four distinct resistance states. During each clock cycle the accelerator performs column‑wise multiplication of the stored weights with a four‑valued input vector, followed by row‑wise analog summation of the results, thereby executing a full MVM operation entirely in memory. The analog front‑end, comprising ADCs, DACs and amplifiers, was developed by TU Munich and integrated into the design, enabling the conversion between digital control signals and the analog computation performed by the crossbar.

Characterisation of the 130 nm array revealed significant improvements over the earlier 250 nm prototype. The electrical behaviour, particularly the programmability of individual cell states, was more reliable, and the variability between cells was reduced. No stuck‑at‑open or stuck‑at‑short defects were observed, and the dominant error mechanism became read‑disturb, where repeated reads slightly alter the stored value. This effect can be mitigated by periodic refresh operations, which are straightforward to implement in the accelerator’s control logic. The overall reliability of the 16 × 16 array thus meets the stringent safety requirements for autonomous vehicle applications.

A comprehensive simulation model of the crossbar was developed in SystemVerilog and SystemC, incorporating the measured electrical parameters and realistic error models. This model enabled the validation of inference for several neural‑network topologies that could not be executed on the physical accelerator due to size constraints. Moreover, it facilitated studies of fault‑aware training (FAT), demonstrating that larger neural networks can be trained to tolerate the residual hardware imperfections, thereby enhancing robustness without sacrificing accuracy.

The project also produced a 4‑kbit RRAM array in 250 nm technology earlier in the program, which served as a test vehicle for scaling the process to 130 nm. The successful scaling, coupled with the development of a CMOS‑compatible back‑end‑of‑line (BEOL) process, demonstrates the maturity of IHP’s RRAM technology for integration into mainstream semiconductor manufacturing. The resulting neuromorphic accelerator, with its compact footprint, low power consumption (well below the 500 W typical of conventional CMOS‑based AI accelerators), and built‑in redundancy and error‑correction mechanisms, represents a significant step toward energy‑efficient AI processing in autonomous vehicles.