The ANDANTE project, funded by the German Ministry of Education and Research under grant number 16MEE0112S, ran from July 2020 to November 2023 and was led by Ferroelectric Memory GmbH (FMC). FMC’s role focused on the development and characterization of non‑volatile memory based on ferro‑electric field‑effect transistors (FeFETs) and on the creation of a Physical Design Kit (PDK) that integrates the FeFET technology into the Cadence Virtuoso design environment. The project was organised into two main work packages. In work package 2 FMC characterised FeFET memory cells and arrays, measured threshold‑voltage distributions, read‑current statistics, and endurance, and produced the PDK that includes transistor symbols, parameter callbacks, and programmable layout cells (PCells). In work package 3 FMC designed a memory macro that serves both as a code and data store and as an accelerator for convolutional neural networks (CNNs). The macro combines an analog front‑end with a digital controller; the digital part was initially intended for a tape‑out but was instead implemented on an FPGA platform. The FPGA design reads data from an existing FeFET test chip fabricated by FMC, processes it, and streams the results to a PC camera, thereby demonstrating real‑time image‑processing capability for edge‑AI applications. Performance measurements of the FeFET cells showed bit‑error rates below 10⁻⁵ in 131 kbit sectors, endurance between 10 000 and 100 000 write cycles, and data retention exceeding 24 hours at 200 °C. Earlier tests on the same technology reported more than 100 million write cycles and 24‑hour retention at 200 °C, confirming the suitability of the 28 nm bulk process supplied by GlobalFoundries. The PDK’s seamless integration with Cadence Virtuoso enabled automated design‑rule checks and facilitated the rapid prototyping of the macro. The FPGA implementation required porting the digital hardware description, developing a custom PCB, and conducting extensive verification, which replaced the planned silicon tape‑out. The collaboration also involved GlobalFoundries as the foundry partner and Cadence as the EDA tool provider, while the project’s objectives aligned with the broader ANDANTE goal of exploring AI‑enabled electronics and edge‑computing technologies. Overall, the project delivered a functional FeFET‑based memory macro with an embedded CNN accelerator, validated through real‑time FPGA testing, and established a robust design flow via the newly created PDK, thereby advancing the feasibility of FeFET technology for future AI‑centric embedded systems.